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    • 专利摘要:
    The invention relates in particular to a method of producing on the same substrate (100) at least one first transistor and at least one second transistor, characterized in that the method comprises at least the following steps: - Realization on a substrate (100) of at least a first grid pattern (200, 200 ') and at least one second grid pattern (300, 300'); - Deposition on the first and second grid pattern (200, 200 ', 300, 300') of at least a first protective layer (500); - Deposition on the first and second grid pattern (200, 200 ', 300) of at least: a first protective layer (500) and a second protective layer (600) overlying the first protective layer (500) and made of a material different from that of the first protective layer (500) and; - Masking the second pattern by a masking layer (700); - Isotropic etching of the second protective layer (600); - Removing the masking layer (700); - Anisotropic etching of the second protective layer (600) selectively to the first protective layer (500).
    公开号:FR3051598A1
    申请号:FR1654556
    申请日:2016-05-20
    公开日:2017-11-24
    发明作者:Nicolas Posseme；Laurent Grenouillet
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    TECHNICAL FIELD OF THE INVENTION
    The present invention relates to the realization on the same substrate of transistors having different characteristics, for example gate oxides whose thicknesses are different. It will find advantageous application the realization of such transistors on a FDSOI type substrate.
    STATE OF THE ART
    For some circuits, it is necessary to produce on the same developed substrate, also called slice or wafer in English, transistors having different characteristics, for example different thicknesses of gate oxide.
    The substrates produced generally comprise a support substrate surmounted by an oxide layer and a semiconductor layer whose thickness is fine. They are called FDSOI (fully depleted Silicon on insulator meaning totally deserted silicon-on-insulator) or PDSOI (partially depleted Silicon on insulator meaning silicon-on-insulator partially deserted) mainly depending on the thickness of the semiconductor layer .
    The transistors that are produced on this type of elaborated substrates have a gate stack comprising in particular a gate usually made of doped silicon or metal, a metal layer and an electrically insulating layer of gate oxide between the active layer and the polycrystalline silicon grid.
    On the same developed substrate, it is possible to produce transistors of a first type having a characteristic different from that of a second type of transistor. For example, transistors of a first type having a first gate oxide thickness and transistors of a second type having a second gate oxide thickness greater than the first thickness may be produced on the same substrate. to operate at higher voltages.
    In order to limit the complexity of the process, many steps are common to the realization of the two types of transistors including the realization of the metal layer, the polysilicon gate, the spacers, the sources and drains.
    The object of the present invention is to propose a solution for reproducibly and simply integrating, on the same substrate, transistors having different characteristics, for example gate oxides whose thicknesses are different.
    SUMMARY OF THE INVENTION
    To achieve this objective, according to one embodiment, the present invention provides a method for producing on the same substrate, for example of semiconductor-on-insulator type, of at least one first transistor and at least one second transistor, the method comprising at least the following steps: - Realization on a substrate for example of the semiconductor-on-insulator type of at least a first grid pattern and at least one second grid pattern; - Deposition on the first and second grid pattern of at least a first layer of protection; - Masking the second pattern by a masking layer; After the masking step: isotropic modification of the first protective layer located on the first pattern by isotropic implantation of ions in the first protective layer so as to form modified portions of the first layer; the second pattern being masked by the masking layer during this isotropic modification; - Removal of the masking layer; Before the masking step or after the step of removing the masking layer: anisotropic modification of the first protective layer by anisotropic ion implantation in the first protective layer, the anisotropic implantation being carried out in one direction; preferred parallel to flanks of the second pattern so as to modify the first protective layer at least on one vertex of the second pattern and outside the first and second patterns while maintaining unmodified portions of the first protective layer on the flanks the second reason; - Selectively etching the modified portions of the first protective layer selectively to unmodified portions of the first protective layer.
    Thus, the method according to the invention makes it possible to produce on the flanks of the second pattern spacers of greater thickness than on the flanks of the first pattern.
    The present invention thus proposes a solution for reproducibly and simply integrating, on the same substrate, transistors having different characteristics.
    It offers a particularly advantageous advantage for the realization on the same substrate of transistors whose gate stacks have insulating layers, typically gate oxides, whose thicknesses are different. In practice, it has been found that, with the known solutions, the performances of the transistors whose gate oxides are thicker are often degraded as they are used.
    Consequently, with the known solutions, the performances and the lifetime of the devices comprising these transistors can represent a barrier to their industrialization.
    In the development context of the present invention, it has been noted that with the known solutions, in the transistor having a gate stack with the thickest gate oxide, the electric field is the highest at the interface between source / drain and spacers and not at the gate oxide level, as was predictable.
    This strong electric field can cause the breakdown of the spacer as the operation of the transistor.
    By providing a thicker spacer on the sidewalls of the gate of the second transistor which must withstand higher voltages, the invention makes it possible to eliminate this risk of breakdown.
    Furthermore, the invention makes it possible to keep on the sidewalls of the gate of the first transistor a thin spacer thickness. The invention thus makes it possible to preserve the performance of transistors whose gate oxides are the finest.
    In addition, the invention has a limited complexity compared to conventional solutions in which the gate spacers on the flanks of the first and second transistors are of identical thickness. In particular, the method according to the invention does not require an additional mask of lithography. In particular, advantageously, the mask level for introducing the difference in thickness on the spacer is the same as that used to induce the gate oxide difference.
    In addition, this method does not require additional overgrafting which could deteriorate the active layer.
    The method according to the invention is thus compatible with the subsequent steps which are conventional to finalize the realization of the transistors.
    Thus, the invention provides an efficient, easily industrializable and inexpensive solution to improve the performance and life of devices with different characteristics, for example transistors whose gate oxides have different thicknesses.
    It is particularly advantageous for producing FDSOI transistors. The invention nevertheless applies in particular to transistors formed on bulk substrates (in English "bulk") or on substrates of PDSOI type.
    Optionally, the invention may furthermore have at least one of the following optional features: According to one embodiment, the first grid pattern is a first grid stack, and the second grid pattern is a second grid pattern. grid stack.
    According to another embodiment, the first grid pattern is a sacrificial pattern and the second pattern is a sacrificial pattern. The method comprises, after said step of selectively etching the modified portions, a step of replacing the first and second sacrificial patterns with patterns respectively forming a first gate stack and a second gate stack. According to another embodiment, each of the first and second grid stacks comprises at least one insulating layer, typically a gate oxide, the thickness of the insulating layer of the second stack being greater than the thickness of the insulating layer of the first stack. According to one embodiment, the thickness of the gate oxide of the first stack is between 0 and 3 nm (10'® meters) and preferably between 0 and 1.5 nm. According to one embodiment, the thickness of the gate oxide of the second stack is between 1.5 and 8 nm, preferably between 2 and 6 nm and preferably between 2 and 3.5 nm. According to one embodiment, the grid pattern is intended to form a gate for the transistor. The grid pattern is then functional. It is then a process that can be described as "gâte first", that is to say in which the grid is carried out beforehand. According to another embodiment, the grid pattern is intended to be removed, after forming the spacers, to then be replaced by a functional grid pattern. The grid pattern is then sacrificial. It is then a process that can be described as "gâte last", that is to say in which the grid is made in a second time. According to one embodiment, the method comprises, after the selective etching step, a step of forming at least one additional layer on the flanks of the spacers of the first and second patterns. According to one embodiment, the thickness of said additional layer is identical on the sidewalls of the spacers of the first and second patterns. According to one embodiment, the anisotropic modification of the first protective layer by anisotropic ion implantation in the first protective layer is carried out before the masking step. Alternatively, the anisotropic modification of the first protective layer by anisotropic ion implantation in the first protective layer is performed after the step of removing the masking layer. According to one embodiment, the substrate comprises an active layer located under the first and second grid patterns and said selective etching is performed so as to etch the modified portions of the first protective layer selectively to the active layer. According to one embodiment, the first protective layer is made of nitride, preferably of silicon nitride (SiN). Alternatively, the first protective layer of a material whose dielectric constant is less than 7 and is preferably selected from the following materials: a carbon-based material (C), SiCO, SiC, SiCN, SiOCN, SiCBN, SiOCH, CBN, BN, SiCBO and SiO2. According to one embodiment, the protective layer is a porous layer. Alternatively, the protective layer is a non-porous layer. According to one embodiment, at least one of the insulating layer of the first pattern and the insulating layer of the second pattern is a gate oxide layer.
    Additionally, optionally, the invention may further have at least one of the following additional features:
    According to one embodiment, the isotropic modification of the first protective layer by isotropic implantation of ions in the first protective layer is performed using an implanter and modifying a direction of bombardment during implantation. .
    Alternatively, the isotropic modification of the first protective layer is performed by isotropic implantation of ions from a plasma.
    In one embodiment, the implanted ions are helium ions or hydrogen-based ions. According to one embodiment, during the isotropic modification, a pressure greater than 100 milli Torr is maintained.
    This makes the implantation more isotropic.
    According to one embodiment, the anisotropic modification of the first protective layer by anisotropic ion implantation in the first protective layer is carried out using an implanter and maintaining a substantially constant bombardment direction during the first protective layer. implantation, this direction being substantially parallel to the sides of the second pattern.
    According to one embodiment, the ions implanted during the anisotropic modification are taken from one or more of the following species: argon (Ar) and fluorinated (F).
    Alternatively, the anisotropic modification of the first protective layer is carried out by anisotropic implantation of ions from a plasma.
    In one embodiment, the implanted ions are helium ions or hydrogen-based ions. According to one embodiment, during the anisotropic modification, a pressure of less than 100 milli Torr is maintained. This makes it possible to avoid deflection of the ions which would be detrimental to the anisotropy of the implantation.
    According to one embodiment, said anisotropic modification of the first protective layer comprises the following steps: placing the protective layer in the presence of a plasma formed from a gaseous mixture formed of at least a first gaseous non-carbonaceous component whose dissociation generates the light ions and a second gaseous component comprising at least one species promoting the dissociation of the first component to form the light ions. In one embodiment, the gas ratio between the first component and the second component is greater than 1:19 and less than 19: 1. The addition of a second component advantageously acting as a dissociation gas (such as argon, helium, xenon, nitrogen), makes it possible to facilitate the dissociation of the first component and thereby promote implantation of said first dissociated component in the protective layer 500, in the form of light ions.
    Preferably, said ratio is between 1: 9 and 9: 1.
    The above characteristics are applicable to isotropic modification if the pressure is sufficient to obtain isotropy of the modification.
    Furthermore, optionally also, the invention may furthermore have at least one of the following optional features: According to one embodiment, said selective etching is a wet etching using a solution based on of hydrofluoric acid (HF) and / or with a solution of phosphoric acid (H3PO4). - Alternatively, said selective etching is a dry etching, preferably performed in a plasma formed from nitrogen trifluoride (NF3) and ammonia (NH3). According to one embodiment, the dry etching comprises: an etching step consisting of the formation of solid salts; a step of sublimation of the solid species. Alternatively, said selective etching comprises: dry etching carried out by placing the modified portions of the first protective layer in the presence of a gaseous mixture, preferably solely gaseous, comprising at least a first component based on hydrofluoric acid (HF); ), hydrofluoric acid transforming into non-volatile residues at room temperature the modified dielectric layer, - only after dry etching: removal of non-volatile residues at room temperature by wet cleaning or thermal sublimation annealing.
    Another aspect of the present invention relates to a microelectronic device comprising on the same semiconductor-on-insulator substrate at least one first transistor and at least one second transistor each having a grid pattern and spacers located on the sides of the patterns. each grid pattern comprising a stack comprising at least one gate and an insulating layer located between the gate and an active layer of said substrate. The insulating layer of the gate stack of the second transistor has a thickness greater than that of the first transistor. The spacers of the second transistor are thicker than the spacers of the first transistor.
    By microelectronic device is meant any type of device made with microelectronics means. These devices include, in addition to purely electronic devices, micromechanical or electromechanical devices (MEMS, NEMS ...) as well as optical or optoelectronic devices (MOEMS ...).
    Optionally, the substrate is of FDSOI, PDSOI or solid ("bulk") type.
    Other objects, features and advantages of the present invention will become apparent from the following description and accompanying drawings. It is understood that other benefits may be incorporated.
    BRIEF DESCRIPTION OF THE FIGURES
    The objects, objects, as well as the features and advantages of the invention will become more apparent from the detailed description of an embodiment thereof which is illustrated by the following accompanying drawings in which:
    FIGURE 1 is a schematic representation of an elaborate substrate comprising grid patterns whose dielectric layers have different thicknesses.
    FIGS. 2 to 9 illustrate steps of an embodiment of the method according to the invention.
    FIG. 10 summarizes certain steps of two examples of method according to the invention.
    The drawings are given by way of examples and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily at the scale of practical applications. In particular, the relative thicknesses of the different layers and films are not representative of reality.
    DETAILED DESCRIPTION OF THE INVENTION
    It is specified that in the context of the present invention, the terms "over", "overcomes", "covers" or "underlying" or their equivalents do not necessarily mean "in contact with". For example, the deposition of a first layer on a second layer does not necessarily mean that the two layers are in direct contact with one another, but that means that the first layer at least partially covers the second layer. being either directly in contact with it or separated from it by at least one other layer or at least one other element.
    With reference to FIGS. 1 to 9, an exemplary method according to the invention will now be described.
    FIG. 1 illustrates a structure from which the steps of the method according to the invention are implemented. This structure includes transistors being formed.
    This structure comprises: an elaborate substrate 100 of semiconductor on insulator (SOI) type. In the illustrated example, this elaborated substrate successively comprises a support layer 101; for example monocrystalline silicon, polycrystalline or amorphous; a dielectric layer 102, usually called buried oxide (BOX for Buried Oxide in English) and a semiconductor active layer 103 for forming a conduction channel of a transistor. The latter is for example silicon (Si), germanium (Ge) or silicon-germanium (SiGe), preferably monocrystalline. - Grid patterns 200, 200 ', 300, 300'. In the illustrated nonlimiting example, the grid patterns 200, 200 ', 300, 300' each form a stack of several layers. These patterns 200, 200 ', 300, 300' are intended to be retained in the final transistors (gate-first method). According to a non-illustrated alternative embodiment, the grid patterns 200, 200 ', 300, 300' are sacrificial patterns which are intended to be removed after the spacers have been made, then to be replaced by another grid preferably forming a stack. (last type process). The invention covers this alternative embodiment.
    In the remainder of the description, which illustrates an embodiment of the first type with reference to the figures, the term "stack" or "pattern" will be used as well.
    Typically, the gate stacks each comprise at least one gate 204, 304 usually made of polycrystalline silicon or metal and an insulating layer 201, 301 usually referred to as a gate oxide situated under the gate 204, 304 and through which a field Electrical will be able to develop to create an underlying conduction channel between source and drain when sufficient voltage is applied to gate 204, 304.
    In the illustrated example, the transistors formed from the patterns 200 and 300 will be NFET type and the transistors formed from the patterns 200 'and 300' will be PFET type. This example is, of course, not limiting to the relative arrangement of N and P type transistors. In the following description and for the sake of brevity, only one of the two types of transistors (NFET in the illustrated examples) will be described and referenced in the figures. The steps described with reference to FIGS. 1 to 9 will nevertheless be applicable to both N-type and P-type transistors.
    Preferably, each gate stack 200, 200 ', 300, 300' also comprises: a metal layer often referred to as a metal gate 203, 303 and situated between the gate 204, 304 and the insulating oxide layer 201, 301 grid; a dielectric layer 202, 302, also called a high-permittivity layer or also called "high-k", that is to say made of a high-permittivity material. This layer is located between the insulating layer of gate oxide 201, 301 and the metal gate 203, 303. - A hard mask 205, 305 of protection which will be removed later to allow the resumption of contact on the gate 204, 304. This hard mask 205, 305, which remains in place after etching the gate 204, 304, is typically made of silicon oxide (SiOa) or silicon nitride (SiN). Its role is to protect the top of the gate 204, 304 from any damage during the completion of the following steps and in particular those of etching spacers. A thin oxide layer can be found between the polycrystalline silicon of the gate and the hard nitride mask.
    Preferably, the gate oxide insulating layer 201, 301 is disposed directly in contact with the active layer 103 forming the conduction channel and directly in contact with the high-permittivity layer 202, 302. Preferably, the metal layer 203 , 303 is disposed directly in contact with the high-permittivity layer 202, 302 and directly in contact with the gate 204, 304.
    According to another embodiment, the metal layer 203, 303 and / or the high-permittivity layer 202, 302 are absent.
    The same elaborate substrate 100 supports a plurality of transistors and therefore gate stacks. For some applications, it is necessary to have transistors whose properties are different. Thus, some transistors must have an insulating layer of gate oxide 301 whose thickness is greater than that of the insulating layer of gate oxide 201 of other transistors.
    FIG. 1 thus represents grid stacks 300, 300 'whose thickness of the insulating layer 301 is greater than that of the insulating layer 201 of the stacks 200, 200'. By way of nonlimiting example, it is thus possible to have on the same developed substrate 100: transistors whose insulating layer of gate oxide has a thickness of between 0 and 1.5 nm. These transistors are known to operate at a voltage Vdd between 0.8V and IV. These transistors are sometimes called SG or G01, without this name being limiting. The thickness of the spacers is measured perpendicularly to the plane containing the flanks 210, 310 of the grids 204, 304, i.e. in this example, in a direction parallel to the main plane in which the substrate 100 extends. This thickness is thus measured horizontally in FIGS. 1 to 9 - transistors whose gate oxide has a thickness of between 2 and 5 nm, and more often between 2 and 3.5 nm. These transistors are known to operate at a voltage Vdd of between 1.5V and 3.5V. Thus the breakdown voltage for these transistors is higher than the maximum voltage applied to the gate oxide. These transistors are sometimes called EG or G02, without this name being limiting. transistors whose gate oxide has a thickness of between 3 and 6 nm are known to operate at a voltage Vdd greater than 3V. Thus the breakdown voltage for these transistors is higher than the maximum voltage applied to the gate oxide. These transistors are sometimes called ZG or G03, without this name being limiting.
    The structure illustrated in FIG. 1 also shows the presence of isolation trench 800 traversing the entire active layer 103 to isolate two adjacent transistors. These isolation trenches 800 extend through the entire thickness of the active layer 103 and into the support layer 101. These isolation trenches are typically made of SiO 2.
    FIG. 2 illustrates a following step during which a conformal protective layer 500 is formed intended to form spacers on the sidewalls 310 of the stack 300, 300 '.
    This first protective layer 500 is a monolayer in this embodiment. Nevertheless, it could be formed of a plurality of layers.
    Typically, for transistors whose gate oxides 301 have a thickness of the order of 3 to 5 nm, the total thickness of this protective layer 500 preferably has a thickness of between 3 and 10 nm and preferably between 4 and 10 nm. and 6 nm.
    Moreover, in order to limit the complexity of the processes and to limit their cost, it is preferable that the spacers of transistors of two different types are made during the same steps.
    This leads to the fact that, in known processes, the spacers of the transistors having thicker gate oxides are also less than 9 nm.
    In the context of the development of the present invention, it has been identified that this thickness often leads to a breakdown at the spacers of the thick gate oxide transistors, thereby deteriorating the reliability and the lifetime of the devices incorporating this type. of transistors.
    The following steps make it possible to remedy this problem by forming thicker spacers on the sidewalls 310 of the stacks 300, the insulating layer 301 of which is thicker, while limiting the complexity of the process.
    This protective layer 500 illustrated is for example nitride, such as silicon nitride (SiN).
    It can be a porous or non-porous material. In the context of the present invention, the term "porous layer" denotes a layer in which the presence of vacuum is greater than 5% and preferably between 5 and 10%.
    Alternatively, the layer 500 may be made of a low-k material, i.e. low permittivity. Its permittivity is less than 7 and preferably less than 4. It then preferably comprises at least one of the following species or a combination of these species: silicon (Si), carbon (C), boron (B), nitrogen ( N), hydrogen (H). It is for example formed in one of the following materials: SiCO, SiC, SiCN, SiOCN or SiCBN. This low-k layer is porous or not.
    The dielectric constant of these layers is measured for example by the conventional method known as the mercury drop.
    The protective layer 500 is obtained by a conformal deposition, that is to say that it has a constant thickness over the entire plate and in particular on the sidewalls 210, 310 and the vertices 220, 320 of the stacks 200, 200 ', 300, 300' grid as well as outside these grid stacks.
    FIG. 3 illustrates a following step during which a masking layer 700 is formed to entirely cover the second gate stack 300 (and thus also the stack 300 'in this example), that is to say the one presenting a thickness of insulating layer (for example of gate oxide) 301 greater than that of the first stack 200. This masking layer 700 is typically a carbon-based layer, preferably resin, deposited full plate, then open at the level of of the first stack 200 by one of the conventional lithography techniques.
    In the context of the present invention, the resin is an organic or organo-mineral material that can be shaped by exposure to an electron beam, photons or X-rays or mechanically. The step illustrated in FIG. 4 aims at isotropically modifying the first protective layer 500 on the first stacks 200, 200 '. For this purpose, this modification step comprises at least one anisotropic implantation 400 of ions in the layer 500, preferably in the entire thickness of the latter.
    This ion implantation 400 is preferably made full plate. The first layer 500 making use of the stacks 300, 300 'is not modified because it is protected by the masking layer 700.
    This isotropic implantation 400 makes it possible to modify the protective layer 500 without spraying it. Thus, it is essentially a chemical modification, the addition of ions in this layer 500 changing the selectivity to the etching of this layer 500. Thus, the modified portions 550 will burn much more easily than the unmodified portions 510. Implantation can be performed: - in a conventional implanter, (beamiine), that is to say with implantation by ion beam;
    An advantage afforded by the use of an implanter is the possibility of modifying the protective layer 500 on the sidewalls 210 of the first stack 200 by bombarding in several inclinations (tilt) the direction of implantation.
    For this type of implantation, the following species will for example be used to modify the protective layer 500: argon (Ar), fluorine (F), oxygen (O) or hydrogen (H). The angle of inclination of the implantation and the energy of the ions will be adapted as a function of the density and the shape of the patterns formed by the stacks 200 of the masking layer 700, as well as according to the thickness of the protective layer 500.
    Typically, the ion beam implanted dose is greater than 1-15 atoms per square centimeter (at / cm 2).
    These implantation conditions are for example determined by simulation using simulation tools of SRIM type (stopping and range of ions matter) or TRIM (transport simulation of ions in matter). These simulation tools can also be used to determine the implantation conditions for plasma implantations which will be detailed below. in a plasma etching equipment. In this case, it will be possible to use a capacitively coupled plasma reactor (CCP) or an inductively coupled plasma reactor (ICP), or an immersion plasma. Plasma ion implantation is an advantageous solution, in particular since it allows precise control of the implanted depth in order to: - implant and thus modify the entire thickness of the protective layer 500; to not implant the underlying layers, in particular the active layer 103 and the grid 204.
    Furthermore, the advantage of the plasma is that there is a chemical modification including implantation H, which makes the removal of the modified layer easier.
    According to an exemplary embodiment, this modification comprises the implantation of hydrogen-based ions (H, H · ", H2", H3 ", etc.).
    In another embodiment, the implanted ions are helium ions (He) or a mixture of helium and hydrogen ions (H / He).
    These ions can come for example from the following gases introduced into the reactor: H2, HBr; NH3.
    In order to obtain an isotropic modification by plasma implantation one can play on several parameters: the pressure. Preferably it is greater than 100 milli Torr. This makes it possible to have a deflection of the ions to reach the flanks 204 of the stacks 200, 200 '. - Temperature. It is preferably less than 100 ° C. which makes it possible to modify the protective layer 500 more effectively. It has been found that above 100 ° C. the implanted H ions desorb which reduces the desired modification effect. - The implanted species. The ions based on H and He allow implantation of the protective layer 500 without spraying the latter and without deposit on the surface of the latter. - We can also draw the bias voltage (bias) and / or the source so as to accentuate the isotropic effect. At the end of this implantation step, the entire protective layer 500 not covered by the masking layer 700 is modified, preferably over its entire thickness. Thus a modified layer 550 is formed on both the top 220 and the sidewalls 210 of the stacks 200, 200 'and between these stacks 200, 200'.
    As illustrated in FIG. 5, the masking layer 700 is then removed. Naturally, this shrinkage is selective of the material of the first modified layer 550 in order to preserve the latter on the first stack 200. When this masking layer 700 is a photosensitive resin, it is for example removed in a capacitively coupled reactor, or inductive or microwave coupling using oxidative (Oa-based) or reductive (H2-based) chemistry. For example, a gas mixture of Na and Ha can be injected into a plasma reactor for etching and then wet cleaned to remove resin residues. This cleaning can be carried out using a solution SCI (NH40H-HaOa). At this stage, the initial thickness of the first layer 500 is retained in its entirety on the stacks 300, 300 '. It is modified on all or part of its thickness on the stacks 200, 200 '.
    FIGS. 6 and 7 are intended to anisotropically modify and etch the first protective layer 500 on the stacks 300, 300 'in order to eliminate or reduce the thickness of this layer 500 on the top 320 of the second stacks 300, 300' all keeping a large thickness of this layer 500 on their sidewalls 310 and without significantly altering the active layer 103.
    FIG. 6 illustrates an anisotropic modification step of the protective layer 500 by ion implantation 450 within this layer in a preferred direction. This direction is parallel to the flanks 310 of the two stacks 300, 300 '. In the illustrated example, this direction is perpendicular to the main plane in which the substrate 100 extends, that is to say a vertical direction in this FIG.
    As for the isotropic implantation 400, this anisotropic implantation makes it possible to modify the protective layer 500 without however spraying it. Thus, it is essentially a chemical modification of the layer 500, the addition of ions in this layer 500 changing the selectivity of the etching of the modified portions 550 relative to the unmodified portions 510 of this protective layer 500 .
    This modification can be performed by implantation using an implanter or from a plasma. These two embodiments and their variants are detailed below: 1. implantation by conventional implants
    A first embodiment consists in implanting ions using implementers usually referred to as "beamiine". In contrast to the isotropic modification, the implantation angle remains constant throughout the implantation. This inclination is parallel to the sidewalls 310 of the stacks 300, 300 'covered with the unmodified protective layer 500.
    For this type of implantation, the protective layer 500 is for example made of nitride, such as silicon nitride (SiN).
    Alternatively, the material of the protective layer is taken from: SiCO, Sic, SiCN, SiOCN, SiCBN, SiCBO, SiOCH, cBN (cubic boron nitride) and SiOa. The protective layer 500 may be of a porous or non-porous material. It has a dielectric constant preferably less than 7.
    The implanted species may be argon (Ar), fluorine (F), oxygen (O) or hydrogen (H). . These species allow a precise implantation. In the next step, the modified portions 550 of the protective layer 500 can thus be removed by dry etching in a selective manner with respect to the non-implanted portions 510 and the active layer 103. a plasma
    Another embodiment is to implant in the protective layer 500 ions from a plasma. Preferably, the implanted ions are light ions. The term "light ions" means ions from materials whose atomic number in the periodic table of elements is low. In a general way all the elements that can be implanted in the material to be engraved, without causing dislocation of its atomic structure such that it would cause a spraying of the latter, and therefore without redeposition of the material etched on the walls of the reactor or the patterns being engraved themselves, are likely to agree.
    Preferably, the implanted ions are light ions such as helium ions (He) or hydrogen-based ions (H, H "^, Hs" ^, etc.) whose atomic numbers are respectively 1 and 2. More generally, the light ions are taken from among species whose atomic number is less than or equal to 10. Only one or more of these species can be implanted. at. First embodiment by plasma implantation
    The modification of the nitride layer by 450 implantation of light ions makes it possible to considerably improve the selectivity of the modified protective layer 550 with respect to the semiconductor material of the active layer 103, typically silicon and vis-à-vis screw of the unmodified protective layer 510.
    The etching which is then carried out in the next step illustrated in FIG. 7 thus consumes the modified protective layer 550 preferentially to the active layer 103 of semiconductor material and to the unmodified protective layer 510. Thus, the risk of consumption Excessive surface active layer 103 of semiconductor material is reduced or suppressed.
    Preferably, the modification of the protective layer 500 retains all or part of the thickness of the layer 500 on the sides of the grid 304. This thickness is preserved, at least in part, during the selective etching. It then defines spacers for the grid stack 300, 300 '.
    This modification mode of the protective layer 500 thus makes it possible to deposit a thickness thicker than desired at the end on the sidewalls 310, then to reduce this thickness by implanting ions from the surface of the layer 500 located on the sidewalls 310 and through only a portion of the thickness of the layer 500. Thus, the thickness of the portion 510 covering the gate 304 is precisely controlled, while avoiding the need to perform a very fine deposition of the initial layer 500.
    Furthermore, this embodiment makes it possible to obtain nitride spacers or of low-k material whose thickness is precise while reducing or even eliminating the problems of known solutions such as the formation of "feet" or excessive consumption. active layer 103 at the base of the grid. Plasma implantation has the advantage of allowing implantation to be continuous in a volume extending from the surface of the implanted layer.
    In addition, the use of plasma allows implantation at lower depths than the minimum depths that can be obtained with implants. Thus, a plasma implantation makes it possible to implement efficiently and relatively homogeneously or at least continuously thin layers that can then be removed by selective etching. This continuity of implantation from the implanted face makes it possible to improve the homogeneity of the modification according to the depth, which leads to a constant etching rate in the time of the implanted layer. Moreover, the increase of the selectivity conferred by the implantation with respect to the other layers is effective from the beginning of the etching of the implanted layer. The plasma implantation thus allows a significantly improved control of the engraving accuracy. Plasma implantation typically allows implanting and then removing thicknesses extending from the surface of the implanted layer and at a depth ranging from 0 nm to a few nm, which is advantageous for precisely controlling the implantation in layers as well. than those deposited to form the spacers. The use of a plasma to modify the layer to be removed is therefore particularly advantageous since it is desired not to entirely remove the protective layer 500 on the sidewalls or to remove a thin and carefully controlled thickness, typically between 1 nm and 5 nm and more generally between 1 nm and 30 nm. The modification step made from a plasma modifies the protective layer 500 continuously from the surface of the protective layer 500 and over a thickness of between 1 nm and 30 nm and preferably between 1 nm and 10 nm. .
    According to a particularly advantageous embodiment, the implantation and the subsequent removal of the protective layer 500 are carried out in the same plasma reactor. A modification of the layer 500 to be removed by plasma implantation thus makes it possible to modify the layer and to etch it in the same chamber, which is very advantageous in terms of simplification, time and cost of the process.
    Also advantageously, the modification of the protective layer 500 by implantation of light ions such as hydrogen (H2) or helium (He) also makes it possible to improve the selectivity of this modified protective layer 550 relative to to the oxide of the semiconductor material. Typically, the modified protective layer 550 is removed while the gate oxide and trenches 800 are not consumed or consumed less.
    Optionally, this method may further have at least any of the following features and steps:
    Advantageously, the implantation is performed so as to modify the entire thickness of the protective layer 500 outside the protective layer 500 disposed on the sidewalls 310 of the grid 304. Thus, the etching removes the entire protective layer 500 with the exception of at least a portion of the protective layer 500 located on the sidewalls 310 of the grid 304.
    Advantageously, the thickness of the modified protective layer 550 on the sidewalls 310 of the gate 304 is zero or less than the thickness of the protective layer 500 before modification by implantation.
    Preferably, the implantation modifies the protective layer 500 uninterruptedly from the surface.
    According to a particular embodiment, the method comprises a single modification step carried out so as to modify the protective layer 500 throughout its thickness on all the surfaces parallel to the plane of a substrate 100 on which the grids 304 rest and to not to modify the protective layer 500 throughout its thickness on the surfaces perpendicular to this plane.
    According to another embodiment, the method comprises several sequences each comprising a modification step and a withdrawal step. During at least one of the modification steps, only a portion of the thickness of the protective layer 500 is changed. Advantageously, the sequences are repeated until disappearance of the protective layer 500 on all the surfaces parallel to the plane of the substrate 100 on which the grid 304 rests. Only the faces parallel to the sides 310 of the grid 304 retain a thickness of protection 500, this thickness has not been modified by implantation. b. Plasma implantation embodiment: Plasma implantation formed from a mixture comprising a gaseous component promoting the dissociation of another gaseous component to form light ions intended to be implanted in the coating layer. protection 500.
    In this embodiment, the step of modifying the protective layer 500 is performed by bringing the protective layer 500 into contact with a plasma formed from a gaseous mixture formed of at least a first non-gaseous component. carbon whose dissociation generates the light ions and a second gaseous component comprising at least one species promoting the dissociation of the first component to form the light ions. The addition of a second component advantageously acting as a dissociation gas (such as argon, helium, xenon, nitrogen), makes it possible to facilitate the dissociation of the first component and thereby promote implantation of said first dissociated component in the protective layer 500, in the form of light ions. The implanted dose is therefore higher without having to increase the maximum implantation depth. This avoids implanting the underlying layers such as the active layer 103. Moreover, a portion of the thickness of the protective layer 500 can be removed from the sidewalls 310 while precisely controlling the thickness that the we keep.
    It is therefore important to find a fair ratio between the content of the first component and the second component in the plasma intended to modify the protective layer 500. Advantageously, the ratio of gas between the first component and the second component is greater than 1: 19 and below 19: 1.
    A lower ratio, which would be the case if the flow rate of the first gas is reduced, would have the effect of limiting the efficiency of the modification of the dielectric film.
    A higher ratio, which would be the case if one increases the flow of the first gas, would have the effect of limiting the effectiveness of the second gas in terms of dissociation.
    Preferably, said ratio is between 1: 9 and 9: 1.
    In the present patent application a ratio between two gaseous components is a ratio relating to the respective rates of introduction of the components into the chamber of the plasma, typically in the plasma reactor. Each flow is usually measured in sccm. Typically a flow rate is measured with a flow meter associated with the reactor.
    It has proved problematic to target a threshold depth of selectivity of the protective layer 500 which is equal to the implantation depth. From this, two problems then arise: either the etching of the modified protective layer 550 is incomplete requiring repeated etching steps until the desired depth is obtained, or the implantation carried out in the protective layer 500 extends beyond beyond the protective layer 500 thereby causing alteration by implantation of the underlying layer such as the active layer 103.
    Thus, this embodiment is based in particular on the fact that the second component forming the plasma is able to act as a dissociation gas vis-à-vis the first component, preferably based on hydrogen. By promoting the dissociation of the first component, ie hydrogen, the density of hydrogen ions in the gas phase is increased. Thus, for the same implantation energy, the density of hydrogen contained in the protective layer 500 by using the method according to this embodiment is greater than that obtained from a plasma containing only hydrogen ( H2).
    Furthermore, and particularly advantageously, the consumption of the modified protective layer 550 by hydrofluoric acid-based cleaning, for example, is close to the depth of the ion implantation in said modified protective layer 550. by controlling the implantation depth in the protective layer 500, it is possible to estimate with a better precision the thickness of the modified protective layer 550 which will be etched after implantation.
    Optionally, the method may further have at least any of the features and steps below.
    According to a preferred embodiment, the first component is selected from hydrogen (H2), silicon nitride (SiH4), hydrogen nitride (NH3) or hydrogen bromide (HBr).
    According to a preferred embodiment, the second component is chosen from helium (He), nitrogen (N2), argon (Ar) or xenon (Xe).
    Advantageously, the flow rate of the first component is between 10 and 1000 sccm (cubic centimeter per minute). Advantageously, the flow rate of the second component is between 10 and 1000 sccm.
    Preferably, the step of modifying the protective layer 500 is performed so as to provide a polarization power or source power, at a frequency between 100 Hz (Hertz) and 5 kHz, with a duty cycle of between 10% and 90%.
    For each of the above-mentioned embodiments based on plasma implantation, the light ions comprise hydrogen-based (H2) ions selected from: H, H +, H2 +, H3 +. According to another embodiment, the light ions comprise ions based on helium (He) or on the basis of helium and hydrogen.
    For each of the above-mentioned embodiments based on plasma implantation, the protective layer 500 is preferably a nitride-based layer such as a silicon nitride layer.
    In another embodiment, the protective layer 500 has or comprises a material having a dielectric constant less than 7 and preferably 4 and preferably less than 3.1 and preferably less than or equal to 2, thereby reducing parasitic capacitance to possibly improve the performance of the transistor. For example, the material of the protective layer is taken from: SiCO, SiC, SiCN, SiOCN, SiCBN, SiCBO, SiOCH, cBN (cubic boron nitride) and SiOa.
    This reduces the parasitic capacitance and consequently improves the performance of the transistor.
    Each of these materials may be porous or non-porous.
    The features and advantages of all the embodiments indicated above for effecting the anisotropic modification of the protective layer 500 also apply to the isotropic modification of the protective layer 500.
    Preferably the isotropic modification will be carried out with the same equipment as the anisotropic modification in order to simplify the process and reduce costs.
    Preferably, for these different embodiments based on plasma implantation, the following parameters will be adjusted in order to obtain an anisotropic implantation and on a precise depth corresponding to the entire thickness of the protective layer 500.
    These parameters are in particular: the pressure prevailing inside the plasma reactor chamber. Preferably, this pressure is less than 100 milli Tor, in order to avoid isotropic implantation; the temperature will preferably be lower than 100 ° C., in order to effectively modify the protective layer 500.
    For all these embodiments, the implementation conditions can be determined by simulation using an SRIM or TRIM tool.
    Thus, at the end of this anisotropic modification step, the protective layer 500 is modified on all the faces of the stacks 200, 200 ', in particular their flanks 210, on the top 320 of the stacks 300', 300 and between the stacks. 200, 200 ', 300, 300'. Some surfaces, in particular those of the stacks 200, 200 ', have thus been modified during the isotropic implantation 400 and during the anisotropic implantation 450. The protective layer 500 is not modified, or at least not is not modified over its entire thickness, at the flanks 310 of the stacks 300, 300 '.
    FIG. 7 illustrates the result of the step of selectively etching the modified portions 550 of the protective layer 500 with respect to the unmodified portions 510.
    For each of the aforementioned embodiments based on plasma implantation, several alternative embodiments for the selective removal of the modified portions 550 of the protective layer 500 are possible.
    Dry or wet etching chemistries mentioned may be used.
    According to one embodiment, the step of removing the modified protective layer 550 is carried out by selective wet etching to said semiconductor material. If the semiconductor material is silicon, then the step of removing the modified protective layer 550 is carried out by selectively wet etching with silicon (Si) and / or silicon oxide (SiO 2) of the trenches. 800 insulation.
    Preferably, the selective silicon etching is obtained using a solution based on hydrofluoric acid (HF) or using a solution based on phosphoric acid (H3PO4). By way of example with a solution based on hydrofluoric acid (HF), the ratio of etch rate between modified SiN and SiN is of the order of 30; for example, the etch rate ratio between modified SiN and SiOa is of the order of 38.
    This makes it possible to entirely remove the modified protective layer 550 without consuming the unmodified protective layer 510 on the sidewalls 310; the active layer 103; trenches 800.
    The performances of the transistors are thus preserved.
    The semiconductor material may also be germanium (Ge) or silicon-germanium (SiGe).
    According to another embodiment, the removal step is performed by selective dry etching to said semiconductor material. Preferably, the step of removing the modified protective layer 550, typically made of silicon nitride, is carried out by selective dry etching with silicon (Si) and / or with silicon oxide (SiO 2). According to one embodiment, the dry etching is carried out in a plasma formed in a confined chamber from nitrogen trifluoride (NFs) and ammonia (NHs).
    Advantageously, the dry etching comprises: an etching step consisting of the formation of solid salts; a step of sublimation of the solid species. This embodiment makes it possible to obtain a very good selectivity of the etching of the modified nitride relative to the unmodified nitride and to the unmodified semiconductor material. In particular, this selectivity of the etching is much greater (typically a factor of at least 10) than that obtained with a solution of HF.
    According to another embodiment, the step of removing the modified portions 550 of the first protective layer 500 modified vis-à-vis the first protective layer 500 unmodified comprises a dry etching performed by bringing into contact with a gaseous mixture, preferably only gaseous, comprising at least a first component based on hydrofluoric acid (HF). The hydrofluoric acid converts the modified portions 550 of the first protective layer 500 into nonvolatile residues, preferably non-volatile at room temperature.
    Advantageously, the step of removing the modified portions 550 of the first protective layer 500 comprises, only after the dry etching, a removal of non-volatile residues at room temperature by wet cleaning or thermal sublimation annealing.
    Particularly advantageously, the present invention allows a selective etching of the modified portions 550 of the first protective layer 500 vis-à-vis a silicon oxide-based layer. The variation range of the parameters of the gaseous HF process making it possible to obtain a selectivity of the modified portions 550 of the first protective layer 500, for example based on silicon nitride (SiN) with respect to the first unmodified protective layer 500 , is more extensive.
    An advantage of the present invention is that the bringing into contact can be carried out in a simple chemical reactor: a hermetic enclosure in which the reactants are introduced and which operates either at room temperature and atmospheric pressure, or at a temperature higher than ambient and at a pressure below atmospheric pressure. The placing in the presence is therefore advantageously not performed in a plasma reactor whose equipment and management is more complex than a chemical reactor. Thus, the gaseous HF is simple to implement compared to a plasma. Indeed, a simple chemical reactor, possibly regulated in pressure and temperature, is sufficient. In the case of a plasma, it would take RF generators and work at a much lower pressure, so the equipment in this case would be much more complex.
    Advantageously, thermal annealing and HF etching are performed during successive and non-simultaneous steps. This makes it possible to prevent the temperature necessary for annealing to be detrimental to the adsorption of HF on the surface of the plate, which would adversely affect the progress of the reaction between HF gas and the modified portions 550 of the first protective layer 500. for example based on SiN.
    In a particularly advantageous manner, this embodiment allows not only a control of the damage that can be generated as a result of ion implantation, but also an improvement in the removal of the modified portions 550 of the first protective layer 500, by proposing a method having a better etching selectivity between the modified portions 550 of the first protective layer 500 and the first unprimed protective layer 500 on the one hand, between the modified portions 550 of the first protective layer 500 and the silicon oxide layer and between the modified portions 550 of the first protective layer 500 and the layer of a semiconductor material, on the other hand. Advantageously, the selectivity of the HF gas process between the modified dielectric layer and the semiconductor material layer is infinite (that is, the HF gas does not etch the semiconductor material).
    Advantageously, this embodiment proposes an infinite selectivity of the modified portions 550 of the first protection layer 500. Thus, this embodiment allows a better control of the critical dimensions. The method according to this embodiment also allows a selective etching of the modified portions 550 of the first protective layer 500 with respect to other unmodified layers for example, avoiding any risk of consuming all or part of a layer based on silicon nitride or a layer based on silicon oxide such as that forming the isolation trenches 800.
    In this embodiment, the method is performed sequentially. The etching, advantageously "dry", of the modified portions 550 of the first protective layer 500, for example of silicon nitride (SiN), is carried out using pure gaseous hydrofluoric acid (no alcohol co-injection). . At the end of the dry etching, non-volatile residues at room temperature (for example, in the form of salts) are present at the modified portions 550 of the first protective layer 500.
    The term "salt" means an ionic solid compound formed of an anion and a cation but whose overall electrical charge is neutral.
    According to a first embodiment, the nonvolatile etching residues can then be eliminated by performing a simple wet cleaning with water. According to another preferred but nonlimiting embodiment, in order to eliminate the non-volatile residues on the surface of the modified portions 550 of the first protective layer 500, annealing is performed after the "dry" etching of the modified portions 550 of the first protection layer 500. This annealing makes it possible to sublimate nonvolatile residues at room temperature, typically solid salts. This method can be used, for example, to replace a "wet" cleaning, for example water-based cleaning. Advantageously, this alternative method (pure gaseous HF followed by annealing) proposes an entirely "dry" process (which does not contain any steps in the liquid phase), which may be of interest for eliminating known problems caused by "wet" etchings. Made for the formation of patterns, for example.
    According to an advantageous embodiment, a prerecuit step is carried out before dry etching based on gaseous hydrofluoric acid. This makes it possible to eliminate the moisture naturally adsorbed on substrates and thus avoids introducing water, which is a proton acceptor, into the etching chamber of the etcher; said chamber comprising hydrofluoric acid (HF). Thus, the pre-annealing step makes it possible to further increase the selectivity between a modified silicon nitride (SiN) layer and a silicon oxide (SiO 2) layer.
    Particularly advantageously, no etching of a silicon oxide (SiO 2) layer can occur since the etching process of a silicon oxide-based layer only works with the simultaneous presence of silicon oxide. hydrofluoric acid and proton-accepting groups (such as alcohol, water). It is therefore by the absence of simultaneous introduction of hydrofluoric acid and proton acceptor groups, that a high selectivity between a modified silicon nitride (SiN) layer and an oxide layer is obtained. silicon (SiO2). This sequential process also shows a high selectivity between an unmodified silicon nitride (SiN) layer and a modified silicon nitride layer.
    Particularly advantageously, the sequential method according to this embodiment offers a better selectivity of etching of the modified protection layer vis-à-vis silicon (Si) and silicon-germanium (SiGe). This method also has a better selectivity of etching with respect to the silicon oxide (SiO 2) forming, for example, the hard mask or the insulation trenches 800 or the unmodified silicon nitride (SiN), in particular thanks to the absence of proton acceptor groups using a process based on pure gaseous hydrofluoric acid. Other known solutions for removing a layer of modified SiN silicon nitride such as liquid phase hydrofluoric acid (HF) or phosphoric acid (H3PO4) do not allow such selectivity towards, respectively, silicon oxide. (SiO2) or unmodified silicon nitride (SiN).
    Advantageously, the parameters of the step of removing the modified portions 550 of the first protective layer 500, in particular the gas ratio between the first component and the second component used during the dry etching, are provided so that the modified portions 550 of the first protective layer 500 may be selectively etched to the semiconductor material layer and to the unmodified first protective layer 500 and advantageously with respect to the silicon oxide layer. It is therefore important to find a fair ratio between the content of the first component and the second component during dry etching for removing the modified portions 550 from the first protective layer 500. Advantageously, the ratio of gas between the first component ( for example, gaseous HF) and the second component (e.g., pure N2) is from 1: 25 to 1: 1.
    A lower ratio, which would be the case if the flow rate of the first component is reduced, would have the consequence of limiting the etching efficiency of the modified portions 550 of the first protective layer 500. A higher ratio, which would be the case if increasing the flow rate of the first component, would have the effect of limiting the selectivity vis-à-vis the unmodified silicon nitride layer and vis-à-vis the silicon oxide layer. In the present patent application, the ratio between two gaseous components is understood to mean a ratio relating to the respective rates of introduction of the components into the chamber of the chemical reactor (when using gaseous HF). Each flow is usually measured in cubic centimeters per minute (sccm). Typically a flow rate is measured with a flow meter associated with each flow of gas entering the reactor.
    Advantageously, the dry etching consumes the modified portions 550 of the first protective layer 500 preferably to the layer of a semiconductor material and the first unprimed protective layer 500. Thus, the risk of excessive consumption of the surface layer of semiconductor material is reduced or even eliminated. The step illustrated in FIG. 8 comprises depositing a second protective layer 600 that is conformal on all the stacks 200, 200 ', 300, 300'. This second protective layer 600, made of a dielectric, may be monolayer or not. Its purpose is to form a spacer 610 on each of the flanks 210 of the stacks 200, 200 'and flanks 310 of the stacks 300, 300'.
    Thus, at this stage, on each of the flanks 210 of the stacks 200, 200 ', a spacer 250 is formed and has a thickness "e 250" referenced in FIG. 8. This thickness corresponds to the thickness of the second protective layer 600 On each of the flanks 310 of the stacks 300, 300 ', a spacer 350 is formed which will have a thickness "e 350" corresponding to the sum of the thicknesses of the unmodified portions 510 of the first protective layer 500 and the thickness of the second protective layer 600.
    Preferably, the second protective layer 600 is a material taken from those mentioned above for the protective layer 500. It may be porous or non-porous. It may be in a material identical to or different from that of the protective layer 500.
    An optional step not illustrated may consist in forming spacers 900 on the sides of the stacks 200 'and 300', that is to say of the PFET type in this example. These spacers 900 are illustrated in FIG. 9. They are made like the spacers 610, by deposition of a third conformal protective layer, and then removal of this layer outside the flanks of these stacks 200 ', 300'.
    In this case: the spacers 250 of the NFET transistors, whose insulating layer 201 of gate oxide is fine, are formed by a portion 610 at least of the second protective layer 600; the spacers 250 'of the PFET transistors, whose insulating layer 201 of gate oxide is fine, are formed by a portion 610 at least of the second protective layer 600 and a portion 900 of the third protective layer; the spacers 350 of the NFET transistors, whose insulating layer 301 of gate oxide is thick, are formed by a portion 610 at least of the second protective layer 600 and by a portion 510 at least of the first protective layer 500 the spacers 350 'of the PFET transistors, whose insulating layer 301 of gate oxide is thick, are formed by a portion 610 at least of the second protective layer 600 and by a portion 510 at least of the first layer of protection 500 and at least 900 portions of the third protective layer 900.
    Other steps can then be implemented to finalize the production of the transistors.
    Among these conventional steps, it will be possible, for example, to provide for the removal of the second layer 600 on the vertices 220, 320 of the stacks 200, 200 ', 300, 300' and between these stacks in order to preserve portions 510, 610 of these layers 500. and 600 only on the flanks 210, 310 of the stacks 200, 200 ', 300, 300'.
    Another step concerns the growth of the source and drain 1200 by epitaxy from the active layer 103 as illustrated in FIG. 9.
    In view of the above description, it is clear that the method according to the invention makes it possible to improve the lifetime of the devices integrating on the same chip transistors whose gate thicknesses are different, without increasing significantly the complexity of the manufacturing process. The invention is not limited to the previously described embodiments and extends to all the embodiments covered by the claims.
    For example we can reverse the order of some steps. In particular, the anisotropic implantation step 450 of the first protective layer 500 may be performed before the step of masking the second stacks 300, 300 '. According to this alternative embodiment, once the anisotropic implantation step 450 of the first protective layer 500 has been performed, the masking step of the second stacks 300, 300 'is then carried out, followed by the isotropic modification step 400. .
    This alternative embodiment is illustrated in FIG. 10 by the dashed arrows.
    The details, examples and advantages of the steps of the embodiment described in detail with reference to FIGS. 1 to 9 apply to this alternative embodiment in which the anisotropic etching step 450 of the first protective layer 500 is performed before masking of the second stack 300. The invention also covers the case where the modified portions 550 of the first protective layer are etched with respect to the unmodified portions 510 of the first protective layer 500 at the end of each modification step 400 and 450. Nevertheless, the embodiments described above with a single selective etching step performed after the two implantations (isotropic 400 and anisotropic 450) are advantageous in terms of cost and simplification of the process. process.
    Although the invention is particularly advantageous for producing on the same substrate transistors whose gate stacks have insulating layers (typically a gate oxide layer) of different thicknesses, this is not limiting. Indeed the invention also applies to the realization on the same substrate of transistors whose gate stacks have insulating layers of identical thicknesses.
    Moreover, in the illustrated embodiments, the gate stack is made prior to the steps of the invention. These figures thus illustrate a method of type gâte first.
    According to another embodiment covered by the invention, the functional grid stack is produced after the steps of the invention. The grid stack on which the first protective layer is deposited thus forms a sacrificial pattern which will be removed once the spacers have been made. This alternative embodiment is thus a last type of process.
    REFERENCES 100 Prepared substrate 101 Carrier layer 102 Dielectric layer 103 Active layer 200 First stack / Pattern 201 Insulating layer of the first stack 202 High-permittivity layer of the first stack 203 Metal grid of the first stack 204 Grid of the first stack 205 Hard mask of the first stack 210 Flank of the first stack 220 Top of the first stack 250 Spacer of the first stack 300 Second stack / Pattern 301 Insulating layer of the second stack 302 High-permittivity layer of the second stack 303 Metal grid of the second stack 304 Grid of the second stack 305 Hard mask of the second stack 306 Cavity 310 Flank of the second stack 320 Top of the second stack 350 Spacer of the second stack 400 Isotropic implantation 450 Anisotropic layout 500 First protective layer 510 Unmodified portion of the first protective layer 550 Modified portion of the first protective layer 600 Second protective layer 610 Second protective layer portion 700 Masking layer 800 Insulation trench 900 Third protective layer 1200 Source / Drain
    权利要求:
    Claims (20)
    [1" id="c-fr-0001]
    1. Method of producing on the same substrate (100) at least one first transistor and at least one second transistor, characterized in that the method comprises at least the following steps: - Realization on a substrate (100) d at least one first grid pattern (200, 200 ') and at least one second grid pattern (300, 300'); - Deposition on the first and second grid pattern (200, 200 ', 300, 300') of at least a first protective layer (500); - Masking the second grid pattern (300, 300 ') by a masking layer (700); After the masking step: isotropic modification of the first protective layer (600) located on the first grid pattern (200, 200 ') by isotropic implantation (400) of ions in the first protective layer (600) to form modified portions (550) of the first layer (500); - Removing the masking layer (700); - Before the masking step or after the step of removing the masking layer (700): anisotropic modification of the first protective layer (500) by anisotropic implantation (450) of ions in the first protective layer ( 500), the anisotropic implantation (450) being effected in a preferred direction parallel to flanks (310) of the second grid pattern (300, 300 ') so as to modify the first protective layer (500) at least on a top (320) of the second grid pattern (300, 300 ') and outside the first and second grid patterns (200, 200', 300, 300 ') while retaining unmodified portions (510) of the first protective layer (500) on the flanks (310) of the second grid pattern (300, 300 '); - Selectively etching the modified portions (550) of the first protective layer (500) selectively to the unmodified portions (510) of the first protective layer (500).
    [2" id="c-fr-0002]
    2. Method according to the preceding claim wherein the first grid pattern (200, 200 ') is a first gate stack and wherein the second gate pattern (300, 300') is a second gate stack, and wherein each of the first and second grid stacks comprises at least one insulating layer (201, 301), typically a gate oxide.
    [3" id="c-fr-0003]
    The method of claim 1 wherein the first grid pattern (200, 200 ') is a sacrificial pattern, wherein the second pattern (300, 300') is a sacrificial pattern, the method comprising, after said etching step selectively modified portions (550), a step of replacing the first and second patterns (200, 200 ', 300, 300') sacrificial by patterns respectively forming a first gate stack and a second gate stack, and wherein each first and second grid stacks comprise at least one insulating layer (201, 301), typically a gate oxide.
    [4" id="c-fr-0004]
    4. Method according to any one of the two preceding claims wherein the thickness of the insulating layer (301) of the second stack is greater than the thickness of the insulating layer (201) of the first stack.
    [5" id="c-fr-0005]
    5. Method according to the preceding claim wherein the thickness of the insulating layer (201) of the first stack is between 0 and 3 nm (10'® meters) and preferably between 0 and 1.5 nm and in which the the thickness of the insulating layer (301) of the second stack is between 1.5 and 8 nm, preferably between 2 and 6 nm and preferably between 2 and 3.5 nm.
    [6" id="c-fr-0006]
    6. Method according to any one of the preceding claims comprising, after the selective etching step, a step of forming at least one additional layer (610) on the flanks (210, 310) of the spacers (250, 350). first and second patterns (200, 200 ', 300, 300').
    [7" id="c-fr-0007]
    A method according to any one of the preceding claims wherein the anisotropic modification of the first protective layer (500) by anisotropic ion implantation (450) of ions in the first protective layer (500) is carried out prior to the step of masking.
    [8" id="c-fr-0008]
    The method according to any one of claims 1 to 6 wherein the anisotropic modification of the first protective layer (500) by anisotropic (450) ion implantation in the first protective layer (500) is performed after the step of removing the masking layer (700).
    [9" id="c-fr-0009]
    A method according to any one of the preceding claims wherein the substrate (100) comprises an active layer (103) located under the first and second grid patterns (200, 200 ', 300, 300') and said selective etching is performed to etch the modified portions (550) of the first protective layer (500) selectively to the active layer (103).
    [10" id="c-fr-0010]
    10. A method according to any preceding claim wherein the first protective layer (500) is nitride, preferably silicon nitride (SiN) or wherein: the first protective layer (500) of a material of which the dielectric constant is less than 7 and is preferably one of the following materials: a carbon-based material (C), SiCO, SiC, SiCN, SiOCN, SiCBN, SiOCH, CBN, BN , SiCBO and SiO2.
    [11" id="c-fr-0011]
    The method according to any one of the preceding claims, wherein the isotropic modification of the first protective layer (500) by isotropic implantation (400) of ions in the first protective layer (500) is carried out using an implanter and modifying a direction of bombardment during implantation.
    [12" id="c-fr-0012]
    The method of any one of claims 1 to 10 wherein the isotropic modification of the first protective layer (500) is performed by isotropic implantation (400) of ions from a plasma.
    [13" id="c-fr-0013]
    13. Method according to the preceding claim wherein the implanted ions are helium ions or hydrogen-based ions, wherein during the isotropic modification is maintained a pressure greater than 100 milli Torr.
    [14" id="c-fr-0014]
    A method according to any one of the preceding claims wherein the anisotropic modification of the first protective layer (500) by anisotropic ion implantation (450) of ions in the first protective layer (500) is carried out using an implanter and maintaining a substantially constant bombardment direction during implantation, this direction being substantially parallel to the flanks (310) of the second pattern (300, 300 ').
    [15" id="c-fr-0015]
    The method of any one of claims 1 to 13 wherein the anisotropic modification of the first protective layer (500) is performed by anisotropic implantation (450) of ions from a plasma, wherein the implanted ions are preferably helium ions or hydrogen-based ions, and wherein during the anisotropic modification a pressure of preferably less than 100 milli Torr is maintained.
    [16" id="c-fr-0016]
    16. Method according to the preceding claim wherein said anisotropic modification of the first protective layer (500) comprises the steps of: placing the protective layer (500) in contact with a plasma formed from a gaseous mixture consisting of at least one first gaseous non-carbon component whose dissociation generates the light ions and a second gaseous component comprising at least one species promoting the dissociation of the first component to form the light ions and in which the ratio of gas between the first component and the second component is greater than 1; 19 and below 19: 1.
    [17" id="c-fr-0017]
    The method of any of the preceding claims wherein said selective etching is wet etching using a hydrofluoric acid (HF) based solution or a solution based on phosphoric acid (H3PO4).
    [18" id="c-fr-0018]
    18. A method according to any one of claims 1 to 16 wherein said selective etching is a dry etching, preferably performed in a plasma formed from nitrogen trifluoride (NF3) and ammonia (NH3) and wherein dry etching comprises: an etching step consisting of the formation of solid salts; a step of sublimation of the solid species.
    [19" id="c-fr-0019]
    19. A method according to any one of claims 1 to 16 wherein said selective etching comprises dry etching carried out by bringing the modified portions (550) of the first protective layer (500) into contact with a gaseous mixture, preferably only gaseous, comprising at least a first component based on hydrofluoric acid (HF), the hydrofluoric acid transforming non-volatile residues at room temperature the modified dielectric layer, - only after dry etching: a withdrawal of non-volatile residues volatile at room temperature by wet cleaning or thermal sublimation annealing.
    [20" id="c-fr-0020]
    20. Microelectronic device comprising on the same substrate (100) at least one first transistor and at least one second transistor each having a grid pattern (200, 200 ', 300, 300') and spacers (250, 350) located on flanks (210, 310) of the patterns (200, 200 ', 300, 300'), each grid pattern (200, 200 ', 300, 300') comprising a gate stack comprising at least one gate (204, 304); ) and an insulating layer (201, 301) located between the gate (204, 304) and an active layer (103) of said substrate (100), wherein the insulating layer (301) of the gate pattern (300, 300 ') the second transistor has a thickness greater than that of the gate pattern (200, 200 ') of the first transistor, characterized in that the spacers (350) of the second transistor are thicker than the spacers (250) of the first transistor.
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    同族专利:
    公开号 | 公开日
    FR3051598B1|2018-10-05|
    EP3246953A1|2017-11-22|
    US20170338157A1|2017-11-23|
    US10026657B2|2018-07-17|
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    法律状态:
    2017-05-31| PLFP| Fee payment|Year of fee payment: 2 |
    2017-11-24| PLSC| Search report ready|Effective date: 20171124 |
    2018-05-28| PLFP| Fee payment|Year of fee payment: 3 |
    2019-05-31| PLFP| Fee payment|Year of fee payment: 4 |
    2021-02-12| ST| Notification of lapse|Effective date: 20210105 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1654556A|FR3051598B1|2016-05-20|2016-05-20|METHOD FOR PRODUCING ON THE SAME SUBSTRATE TRANSISTORS HAVING DIFFERENT CHARACTERISTICS|
    FR1654556|2016-05-20|FR1654556A| FR3051598B1|2016-05-20|2016-05-20|METHOD FOR PRODUCING ON THE SAME SUBSTRATE TRANSISTORS HAVING DIFFERENT CHARACTERISTICS|
    US15/599,663| US10026657B2|2016-05-20|2017-05-19|Method for producing on the same transistors substrate having different characteristics|
    EP17171987.5A| EP3246953B1|2016-05-20|2017-05-19|Method for forming, on a single substrate, transistors having different characteristics|
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